1. Field
This disclosure relates generally to forming semiconductor devices, and more specifically, to forming semiconductor packages having more than one device.
2. Related Art
It is desirable to provide semiconductor packages that include multiple processor and/or memory die. One manufacturing process includes forming electrical contacts on both sides of a substrate (i.e., double sided build up or 3D (three dimensional) structure. To form a 3D structure, thru vias are formed within a substrate to provide connections between the top surface and the bottom surface of a substrate. The thru vias can be difficult to manufacture and may have electrical and mechanical weaknesses. During the build up process, residual stresses are created, which causes panels to undesirably warp. In addition, the cost of the double-sided build up is high due to the many processing steps of the process. Additionally, dielectric material used to retain the die in the cavity may crack during manufacturing processes such as wire bonding. Hence, a need exists for a method to form a 3D structure, that does not have the disadvantages of the prior art.